The present invention relates generally to shifters and, more particularly, to a shifter for performing an arithmetic right shift operation based on shift data.
FIGS. 5 and 6 show a conventional shifter. A shifter array 5 moves data to the right by a bit width specified by shift data. As shown in FIG. 6, the shifter array 5 receives data (to be shifted) at its inputs D5-D0 and shift data at its inputs SF5-SF0 and outputs shifted data at its outputs SD5-SD0. The shifter array 5 includes six groups of six N-channel MOS transistors 600-605, 610-615, 620-625, 630-635, 640-645, and 650-655, which operate as transmission gates.
Individual gates of the transistors 600-605, 610-615, 620-625, 630-635, 640-645, and 650-655 are connected to the inputs SF0, SF1, SF2, SF3, SF4, and SF5, respectively. Individual sources of the transistors 600, 610, 620, 630, 640, and 650; 601, 611, 621, 631, 641, and 651; 602, 612, 622, 632, 642, and 652; and 603, 613, 623, 633, 643, and 653; and 604, 614, 624, 634, 644, and 654; and 605, 615, 625, 635, 645, and 655 are connected to the outputs SD0, SD1, SD2, SD3, SD4, and SD5, respectively. Individual drain of the transistor 600 is connected to the input D0. Individual drains of the transistors 601, and 610 are connected to the input D1. Individual drains of the transistors 602, 611, and 620 are connected to the input D2. Individual drains of the transistors 603, 612, 621, and 630 are connected to the input D3. Individual drains of the transistors 604, 613, 622, 631, and 640 are connected to the input D4. Individual drains of the transistors 605-655, 614-654, 623-653, 632-652, 641-651, and 650 are connected to the input D5.
In operation, by bringing a bit of shift data SFi (i=5-0) to a high level "H", data applied to the inputs D5-D0 is shifted to the right by i bits and presented at the outputs SD3-SD0. Where the data applied to the inputs D5-D0 is arithmetic data, the i bit right shift operation requires a sign extend facility for the bit positions higher than the SFi bit position.
As shown in FIG. 6, transistors 615, 624-625, 633-635, 642-645, and 651-655 enclosed by a dashed line are provided to constitute a sign extend facility. That is to say, suppose that data "101000" is applied to the inputs D5-D0, the most significant bit (MSB) of the data is "1" indicating that the data is a negative number. When shift data "000100" is applied to the inputs SF5-SF0, 2-bit right shifted data "001010" is obtained unless the transistors enclosed by the dashed line are provided. The MSB of the shifted data is "0" indicating that the result is positive. With the transistors enclosed by the dashed line, however, the shifted data is "111010" and the MSB is "1" indicating that the result is negative. Thus, to propagate the MSB of data for performing an arithmetic right shift operation, the conventional shifter of FIG. 6 requires a sign extend facility, resulting in the increased number of transistors in the shifter array.